For the ESD test engineer one of the most frustrating challenges is charged device model (CDM) testing very small integrated circuits. During field induced CDM testing, following the joint JEDEC/ESDA CDM standard JS-002  the device under test (DUT) is placed “dead bug” position on the field plate, as shown in Figure 1. The DUT is held in place by vacuum through a small hole in the field plate. For large devices, with flat tops, this method works well. As will be discussed below, this does not work well with small devices, and testing can be an exercise in frustration. Heightening the frustration is that the small devices almost never fail CDM, leaving the test and product engineers wondering why are we going through all this hassle. In this blog I will review some of the challenges of testing small devices, discuss why testing of small devices still should be done, note some of the ways test engineers have addressed the problems, and discuss changes to the latest version of JS-002 which can reduce the amount of CDM testing of small devices.
2 Challenges of Small Device CDM Testing
Small devices, with very small area, will have a very small vacuum hold down force, while the force of the pogo pin when it touches the DUT will not change with DUT size. The result for a small ball grid array (BGA) package, if the pogo pin does not touch a ball in the exact center the DUT is pushed to the side and subsequent pogo pin approaches will be misaligned. The problem is more difficult for some classic package types such as SOT-23 (small outline transistor) packages. Figure 2 illustrates how the pogo pin touching the pins of a SOT package will have considerable leverage, making if very likely to dislodge the DUT during testing.
Additionally, JS-002 requires that the area of the DUT be at least 4 times the area of the vacuum hole. If this requirement is not met, the DUT must be placed away from the vacuum hole. Other means of supporting the DUT must then be used.
3 Methods for CDM Testing of Small Packages
A variety of techniques have been used to stabilize packages during CDM testing.  One of the most popular is to use some kind of physical support, such as a hole cut in thin FR-4 to anchor the package in place, as illustrated in Figure 3. This method can be effective, but it is a challenge to create the cutout in the FR-4. Too large an opening and the DUT will not be well supported. Too small an opening and the DUT will not sit flush with the Field Plate surface, resulting in an invalid CDM test.
Another method that is popular with very small devices, such as chip scale packages, is the use of a conversion board. The conversion board is a small circuit board designed specifically for the DUT to be tested. The conversion board serves to make the tiny package mimic an easy to test package such as a dual inline package (DIP). The use of a conversion board makes the actual CDM testing very easy, but there are two disadvantages. First of all is the considerable time and effort of designing and building the conversion board. Secondly, how well does the DUT, mounted on the conversion board, represent the true CDM characteristics of the DUT. It is often the case that the capacitance between the Field Plate and the DUT plus conversion board is considerably greater than the capacitance of what the DUT to Field Plate would be. This can result in a more severe CDM test than if CDM could be conducted on the DUT alone. An addition change in the CDM test behavior is the conversion board will add considerable inductance to the stress path, changing the characteristics of the CDM stress. With those caveats, it is useful to note that I don’t know of any instances in which the use of a conversion board during CDM testing yielded such erroneous results that it led to field failures due to CDM weakness.
4 Why CDM Test Small Devices
Experience has shown that small devices very seldom, if ever, fail CDM testing. This makes technical sense. In a previous blog post, “CDM Dependence on Device Capacitance”, I discussed how the amount of charge in the CDM pulse gets very small for extremely small devices. This leads inevitably to the question, why CDM test small devices? That same blog post also points out that as the DUT capacitance gets very small, the CDM pulse width gets very narrow. The result is that the peak CDM current does not become vanishingly small, and peak current is often considered the cause of CDM failures.
The joint JEDEC/ESDA CDM working group, which maintains the JS-002 CDM test method, formed a task group, which I led, to consider placing a lower limit on package size for CDM testing. After considerable discussion and consideration of the continuing shrinking of feature sizes in integrated circuit, none of the members of the task group were able to defend a specific size or capacitance below which CDM testing is no longer needed. The task group did define a procedure to allow CDM testing to be eliminated for devices with a DUT to Field Plate capacitance below a technology dependent CSMALL value, if a set of strict criteria are met. This procedure will be discussed in the next section.
5 JS-002 Small Package Procedure
In the latest version of the joint JEDEC/ESDA CDM standard, JS-002, , there is a new option that can be used to reduce testing of small packages. The new procedure only applies to groups of products made in the same technology. The same technology includes the following:
- The same wafer fabrication flow
- The same design rules
- The same ESD protection design
- The same ESD design rule checks.
If the following procedure is followed it is possible to eliminate CDM testing for devices with DUT to Field Plate capacitance less than an experimentally determined CSMALL for the technology. CSMALL for the technology is determined with the following procedure.
- Select 5 devices in the technology
- Determine the CDUT for each of the 5 devices
- CDUT is the DUT to Field Plate capacitance
- CDUT can be determined by measurement or 3D field calculation
- Determine the CDM withstand level of the 5 devices
- Determine, CSMALL, the CDUT below which the CDM withstand level is over 1000 V
- See Figure 4
Once CSMALL has been determined, further devices in that technology need not be tested if they meet all the requirements for being included in the technology and the device has been tested and passed the HBM requirements for the technology. Devices that have not been CDM tested based on the above criteria are assigned a CDM withstand level of 750 V. Note: the requirement for doing HBM testing is not because there is a correlation between CDM robustness and HBM robustness. It is simply to ensure that ESD protection elements have been included in the design.
CDM testing of very small integrated circuits can be challenging, because the small size makes them difficult to hold in place using the traditional vacuum hole method. Methods to improve the testability of small devices include the use of FR-4 templates to hold the DUT in place and mounting the DUT on a conversion board to simplify device handling. While most small devices have very high CDM robustness levels, it is not possible to eliminate testing all together because peak current during a CDM test remains high, even for very small packages. Recent changes to JS-002 have allowed elimination CDM of testing of small devices within a device technology if the device’s CDUT is less than the experimentally determined CSMALL for the technology.
- ANSI/JEDEC/ESDA JS-002-2018, “ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Charged Device Model (CDM) – Device Level”
- M. Johnson, R. Ashton and S. Ward, “FCDM measurements of small devices”, 2009 EOS/ESD Symposium.