Two Pin versus Matrix HBM Testing

1 Introduction

This blog will discuss the differences and advantages of two popular types of Human Body Model (HBM) testers for evaluating electronic components for ESD robustness, two pin and matrix based testers. In a future blog I will discuss setting up pin combinations with a two pin tester.

HBM [1] is the most popular electrostatic discharge (ESD) test method for electronic components such as integrated circuits, transistors, diodes and other electronic components to ensure that they have sufficient ESD robustness to survive in an ESD controlled manufacturing environment. In earlier blogs I have discussed the HBM current waveform, tester parasitics, and pin combinations. If you are not familiar with those topics, a quick read of those blogs would be very helpful in understanding the comparison of two pin and matrix-based testing.

The title of this blog, Two Pin Versus Matrix HBM Testing, could be misinterpreted. In this article two pin refers to a tester which has only two pins or terminals, a stress terminal (Terminal A) and a return terminal (Terminal B). It could also be interpreted as testing one pin versus a single other pin. Within the HBM field, and in this article, that type of testing is referred to as pin pair testing. To avoid this confusion, we will first define the terms that will be used in this blog, and then expand upon the definitions and discuss the advantages and disadvantages of the two types of testers.

2 Definitions

These definitions are for the purpose of this blog and are not “official” JS-001 HBM standards definitions. It is also good to note that in HBM testing Terminal B is often referred to as ground. In most cases that is not strictly true. HBM tester often have a resistance in the range of 50 to 100 ohms between Terminal B and true system ground to prevent reflections.

  • Pin Pair Testing: HBM testing in which one pin of the device under test (DUT) is stressed, terminal A, versus a second signal pin which is grounded, terminal B.
  • Ganged Pin Testing: HBM testing in which multiple pins on the DUT are connected to terminal B, while terminal A is stressed. (Note; this is a term I invented for this blog to distinguish this type of testing from pin pair testing.)
  • Two Pin HBM Tester: an HBM tester which has only two terminals. An A terminal which supplies the stress pulse and B terminal.
  • Manual HBM Tester: an HBM tester in which the DUT is inserted in a socket, but requires manual connections and jumpers to connect the A and B terminals of the pulse source to the DUT
  • Matrix HBM Tester: an HBM tester in which a relay matrix is used to connect a single pin to terminal A, the stress terminal, and one or more pins to Terminal B, the ground terminal.
  • Low Parasitic Tester: an HBM tester is considered to be low parasitic if tying multiple pins together does not distort the HBM waveform

3 Expanding on the Definitions

3.1Testing Styles

3.1.1 Pin Pair Testing

Pin pair testing is probably the “purest” form of HBM testing. If all possible paths between pins were covered with pin pair testing any weak paths would be discovered. It would also seem to be the easiest to perform diagnostics on if there is a failure. All current enters one pin and exits through another single pin.

In the earliest days of HBM testing all testing was probably two pin testing. As the number of device pins increased a major limitation soon emerged with regard to two pin testing, doing all possible pin combinations takes a long time.

3.1.2 Ganged Pin Testing

One of the solutions to the long time that two pin testing takes is ganged pin testing. Rather than performing all pin combinations, a single pin on Terminal A could be stressed versus a number of similar pins on Terminal B. This led to the traditional pin combinations in Table 2B of JS-001 [1]. Single pins are stressed on Terminal A, versus pins shorted (ganged) together on Terminal B. Rather than stressing a single pin versus every power and ground pin individually, groups of power and ground pins connected together in the package or on the die are also shorted together in the tester. To find possible weak links between non power pins, each Input or Output pin was stressed to all other Input and Output pins tied together. This method significantly reduced the number of stressed to a device and improved test time considerably. With this type of testing the actual current path of each stress is less well defined.

3.2 Tester Types

3.2.1 Two Pin Testers

Two pin testers are both the oldest and newest type of HBM tester. A two pin tester can only perform pin pair testing. The very earliest HBM testers were probably two pin testers, a power supply, an RC(L) network, a switch and probably clip leads to the DUT. Two pin testers have never truly gone away, and can be very useful for low pin count devices. The ETS 910 existed for many years, and its replacement the ETS 9910, are essentially two pin testers, using a pair of short leads to connect the pulse source to the DUT.

The newest breed of two pin testers is represented by the Grund Technical Solutions Pure Pulse HBM system. Rather than clip leads, the Pure Pulse system uses RF wafer probers to connect to the device under test, as shown in Figure 1. The wafer probers, with 50 ohm impedance to within millimeters of the DUT, ensure that the waveform is delivered to the DUT with minimal distortion and vanishingly low parasitics. The Grund system can also accurately measure the current through the DUT and voltage across the DUT on each HBM pulse. This can be very helpful in diagnosing device functionality and any transformation to a damaged state. [2] The use of robotic wafer probers with the Pure Pulse system facilitates fully automated HBM testing for both packages and at wafer level. The Grund Pure Pulse system is heavily used by Minotaur Labs for both HBM and transmission line pulse (TLP) testing.

Figure 1 Wafer probers from a Pure Pulse HBM system contacting a ball grid array package

3.2.2 Manual HBM Testers

In manual HBM testers the DUT is placed in a socket. Jumpers or specialized pins can be used to connect a single, or multiple pins to Terminal B, while a jumper or other connection is used to connect Terminal A to a single pin. These systems can be useful for low pin count devices, especially in a laboratory only doing occasional HBM testing. A classic example is the IMCS 700, later manufactured by Oryx as the M700. Grund Technical Solutions’ Titan ESD tester is a recent addition to the manual tester environment.

3.2.3 Matrix Based HBM Testers

The high pin counts on modern integrated circuits and the lager number of pin combinations called out by the HBM standards, even with pin ganging, suggests the need for automation. The relay matrix based HBM tester is the logical evolution of this need. A matrix of relays allows any single pin of a DUT inserted into the tester’s socket to be connected to Terminal A and one or more pins to be connected to Terminal B. The use of a relay matrix to complete the A and B connections allows for fully automated testing. The Thermo Fisher MK1, MK2 and MK4 family of testers is one of the most widely used examples of relay matrix based HBM testers. Minotaur Labs performs its relay matrix based testing on an MK2.

3.3 Low Parasitic Tester

In a previous blog post I discussed in some detail the issue with tester parasitics, but I will review here. There have been a number of reports that tester parasitics can cause false failures in matrix based HBM testers [3, 4) and the problem was studied in detail by Chaine et al. [5].  Figure 2 shows a schematic that explains how parasitics in an HBM tester can change waveform properties. Many high pin count devices have multiple pins shorted together for power or ground. In a relay matrix based tester, unless a special test fixture is used, each of these pins will be connected to a channel on the matrix. Even if the relay to a pin is not closed, the relay has capacitance across its terminals. This can distort waveforms as shown in the simulated waveforms in Figure 3. The waveform that exits the DUT pin, IT-B, differs considerably from the injected HBM waveform, IT-A, due to the transient currents to the parasitic capacitors, IPAR. Note that the issue with tester parasitics does not just depend on parasitics on the Terminal B side. Tester channels tied together on the A side can also modify waveforms. Inputs and Outputs are also affected. Stress to an IO will often forward bias diodes to power or ground. If the power or ground group has multiple pins the tester parasitics can distort waveforms in this case also. This was shown in [4].

Figure 2 Schematic to explain tester parasitics.

Figure 3 Terminal A, Terminal B, and Parasitic Current in a simulation with 32 channels tied together in the package.

4 A Best Way for HBM Testing?

The goal of HBM testing following the JS-001 test standard is to get a reliable, repeatable and reproducible measure of the robustness of an integrated circuit during manual handling in an ESD controlled environment.  It is also desirable to have a well-defined current path for easy diagnosis when failure levels are below expectation. These goals are easiest to obtain with pin pair testing with a low parasitic HBM tester.

Pin pair testing can be done with any HBM testers. With a matrix based tester the stress waveforms can differ substantially from the intended HBM waveform, as discussed in the section on tester parasitics. With pin pair testing on a matrix based tester it is true that all current enters by a single pin and eventually exits by a single pin. The current paths between those two pins can be very complex in a matrix based testers, since all pins have parasitic capacitances connected to them. Currents can flow out of, and then back into the DUT as parasitic capacitances charge and then discharge. In recent years some manufacturers of matrix based testers have redesigned the testers to reduce parasitic capacitances. This allows the Terminal B current waveform to stay in specification with higher numbers of pins tied together by the device under test, as well as reducing currents in pins not directly tied to Terminal A or Terminal B. However, for larger pin count devices, with more pins tied together in the package, Terminal B waveforms will still go out of specification and current paths within the device under test will still be hard to understand.

Pin pair testing can also be done on manual HBM testers. In many cases manual tester can be considered “true” low parasitic HBM testers. Manual testers, with their generally low pin counts, typically have large spacings between the traces leading to different pins, resulting in very low capacitance between different pins.

At Minotaur Labs we have found pin pair testing with the Grund Pure Pulse HBM system to be the most straight forward method for performing pin pair HBM testing. The inherently low parasitic nature of the system ensures repeatable, in specification, waveforms and the robotic wafer probers allow automated testing at both package and wafer level. The Grund tester also allows waveform capture during each pulse, which can be very useful during failure analysis. [2]

5 Is There a Place for Matrix Based Testing?

In short, YES! Matrix based testers have, and will continue to serve the electronics industry well. They have uncovered untold numbers of designs that were weak for HBM robustness. Using JS-001 pin combinations in either Table 2A or 2B, matrix based testers can perform HBM testing in an efficient and thorough manner. There have, however, been multiple instances that the parasitics that distort HBM waveforms have caused false failures. These false failures have consumed considerable resources in time and engineering effort. On the other hand, I know of no instances of a worse problem, false passes that have led to high yield loss due to a device with weak HBM levels getting into high volume manufacturing.

6 Conclusion

Pin pair HBM testing with an automated two pin tester, with voltage and current capture on each pulse provides the cleanest waveforms, easy to understand current paths and built in diagnostics. Matrix based HBM testing will, however, continue to be a valuable tool in the electronics industry for many years to come. Manual HBM testers are also a valuable tool for low pin count devices and in test laboratories with a low volume of HBM testing. In a future blog I will discuss setting up the pin combinations using a two pin tester, such as the Grund Pure Pulse system.

7 References

[1] ANSI/ESDA/JEDEC JS-001-2017, For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) – Component Level

[2] Robert Ashton, Stephen Fairbanks, Adam Bergen, and  Evan Grund, “Electrostatic test structures for transmission line pulse and human body model testing at wafer level”, 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS).

[3] W Anderson, et.al. “Cross-Referenced ESD Protection for Power Supplies”, EOS/ESD Symposium, 1998.

[4] H. Kunz, R. Steinhoff, C. Duvvury, G. Boselli, and L. Ting, “The Effect of High Pin-Count ESD Tester Parasitics on Transiently Triggered ESD Clamps”, EOS/ESD Symposium, 2004.

[5] M. Chaine et.al., “HBM Tester Parasitic Effects on High Pin Count Devices with Multiple Power and Ground Pins”, EOS/ESD Symposium, 2006.

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