# 1 Introduction

In a previous blog “Field Induced CDM Explained” I discussed what happens during the CDM test. This included the sequence of events as voltage is applied to the field plate, how the potential on the device under test (DUT) tracks the field plate, and how the DUT actually becomes charged when the pogo pin “discharges” the DUT. The difference between single pulse and dual pulse test sequences was also explained. This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance. If you are unfamiliar with how the DUT potential is controlled by field induction during CDM testing it is suggested to read the earlier blog, “Field Induced CDM Explained” first. In this discussion we will start from the situation in which the Field Plate is at an elevated voltage and the DUT has a potential close to the Field Plate potential.

We will see several CDM properties in this blog:

• For small devices with small capacitance between the DUT and Field plate
• The initial current pulse gets very narrow but,
• The peak current does NOT become negligible
• For large devices with large capacitance between the DUT and Field Plate
• The current pulse becomes much broader
• The peak current and other properties saturate for large devices

# 2 CDM Circuit Diagram

Figure 1 shows a diagram of a field induced CDM (FICDM) tester on the left and an equivalent circuit superimposed on the right. This three-capacitor model for the CDM tester was discussed by Montoya and Maloney  and will be used in the present discussion. A more advanced, 5 capacitor model was introduced by Atwood et all in 2007.  The 5-capacitor model includes capacitance to the tester chassis and helps explain waveshape after the main pulse. The 5-capacitor model was a significant contribution to understanding of CDM, but is not needed for the current discussion. We will, however, use the capacitance values as determined by Atwood as well as his arc resistance value in the discussion.

The three capacitors in the 3-capacitor model are CDUT, the capacitance between the DUT and the Field Plate, CDG, the capacitance between the DUT and the Ground Plane, and CFG, the capacitance between the Field Plate and the Ground Plane. All three of these capacitances change as the size of the DUT varies. Figure 1 Field Induced CDM tester and equivalent circuit

The easiest capacitance to understand is CDUT, since it is primarily a parallel plate capacitor. In the simulations presented here, with one exception, the DUT is a round coin module, similar to that used as the calibration module in the JS-002 CDM test standard . In a real integrated circuit, the DUT capacitance would be the integrated circuit die’s capacitance to the field plate as well as the capacitance of all interconnect traces or lead frame to the field plate. As the physical size of the DUT increases CDUT will increase. At larger sizes CDUT will be roughly proportional to the DUT area. At small sizes, however, CDUT does not approach zero, since at the smallest sizes fringing field capacitance will dominate.

Similarly, as DUT size increases CDG will increase. At large sizes CDG will always be considerably less than CDUT because the length of the pogo pin is always much larger than the thickness of the Field Plate dielectric. For very small DUT sizes CDG will reach a minimum value, because the DUT to pogo pin capacitance at the time of the CDM arc creates a lower limit for CDG.

CFG also changes in magnitude as the DUT size varies. As the DUT gets larger it creates a shield between the Field Plate and Ground Plane, reducing CFG. In the limiting case where the DUT size is larger than the 2.5 inch (63.5 mm) square ground plane direct field lines between the Field Plate and the Ground Plane will be largely blocked.

To gain insight into the CDM behavior, the circuit in Figure 1 was simulated in LTSpice and the circuit is shown in Figure 2. Values of the three capacitors for a variety of DUT sizes were obtained from the values determined by Atwood  and are shown in Table 1. All of the capacitance values were measured by Atwood, except for CDG which was calculated. CDG also includes the pogo pin to DUT capacitance which was estimated by Wallash and Levit  from arc length. As discussed above, the pogo pin to DUT capacitance puts a lower limit on CDG. Figure 2 LTSpice circuit depicted for the 173 pF DUT

 Module Type CDUT (pF) CDG (pF) CFG (pF) Initial DUT V ESDA 0.29 0.31 11.94 241.7 ESDA 0.51 0.31 11.94 311.0 ESDA 0.83 0.33 11.93 357.8 ESDA 1.38 0.36 11.9 396.6 ESDA 2.53 0.44 11.83 425.9 ESDA 3.19 0.44 12 439.4 ESDA 23.7 1.81 10.68 464.5 41mm X 41mm IC 69 2.36 8.09 483.5 JEDEC 173 2.42 8.04 493.1 JEDEC 246 3.39 7.35 493.2 JEDEC 435 7.4 5.01 491.6 JEDEC 975 15.5 0 492.2

Table 1 Capacitance values from Atwood and calculated initial voltage for simulation. The ESDA modules consisted of a copper film on a thin piece of circuit board, similar to those used in the ESDA CDM standard. The JEDEC modules were round coins, similar t those used in the old JEDEC CDM standard. Both the ESDA and JEDEC standards have now been replaced by JS-002 which uses JEDEC type coin calibration modules. The integrated circuit was a 41 mm X 41 mm BGA with a metal heat sink on the top of the package.

Also, following Atwood, a value of 20.5 ohms was used for the combined 1-ohm sense resistor and spark resistance. The spark resistance was included as the on resistance of the relay. The value of inductance of 8 nH is somewhat larger than used by Atwood in his simulations, but the larger value better matches the waveform parameters in the FICDM standard JS-002 . Table 1 also includes the calculated initial DUT voltage used in the simulations. The initial voltage was calculated from the series capacitance of CDUT an CDG with 500 V across the two capacitors.

# 3 Waveform Results

Two simulated current waveforms are shown in Figure 3, for 3.19 pF and 173 pF modules, with a Field Plate voltage of 500 V. As would be expected, the CDM pulse for the smaller capacitance is smaller than the pulse for the larger capacitance. The small capacitor pulse width is also considerably narrower and less damped than for the large capacitor. What is surprising is that the despite the capacitance ratio of 68 between the two, the peak height varies by less than a factor of 2. The seemingly small difference between the waveforms can be understood if we consider how the CDM pulse is simply a redistribution of charge between the three capacitors when the DUT is grounded. The magnitude of the waveforms depends on relative values of the capacitors to each other, the difference between the state of voltages and charges on the capacitors before the CDM pulse, and the state of the voltages and charges on the capacitors just after the CDM pulse. While state of the voltages in the CDM system before the pulse are well understood, the voltage state just after the pulse are seldom considered. Figure 3 Simulated waveforms for CDUT 3.19 pF and 173 pF

Figure 4 shows the simulated DUT and Field Plate voltages, as well as the voltage across the CDUT capacitor, VCDUT, for the current pulses shown in Figure 3. The voltage on the DUT behaves similarly for the two DUT capacitances. The voltage starts off high, close to the charging voltage on the Field Plate, and drops to zero within 5 ns. The magnitude of the behavior for the Field Plate voltage and the voltage across CDUT are substantially different in magnitude, however.

For the 3.19 pF DUT the Field Plate voltage drops about 100 V while the voltage across CDUT increases from about 60 V to 400 V. In contrast, for the 173 pF DUT the Field Plate voltage drops by about 470 V while the voltage across CDUT increases from 7 V to just 29 V. The explanation is simple. For the 3.19 pF DUT the capacitor CFG is substantially larger than CDUT and can provide ample charge to CDUT when the DUT is grounded, while maintaining a high voltage on the Field Plate. For the 173 pF DUT the combined capacitances of CDG and CFG is 10.5 pF and just a small fraction of CDUT. The charge stored on CDG and CFG are therefore only able to change the voltage across CDUT a small amount, while the capacitor CFG is almost totally discharged. Figure 4 DUT and Field Plate voltage as a function of time for a DUTs with 3.19 pF and 173 pF values of CDUT

# 4 Parameter Dependence on CDUT

The amount of charge, and therefore the amount of current, in the CDM stress pulse depends on the relative sizes of the three capacitors. Figure 5 shows the simulated total charge in a CDM pulse as a function of CDUT. In the insert to Figure 5 a linear scale is used for the capacitance and it shows that for very low capacitance the charge increases approximately linearly with CDUT. As CDUT’s value approaches the value of CFG the amount of charge saturates. For larger values of CDUT a logarithmic scale is used for CDUT to show how the behavior for large CDUT Figure 5 Simulated total charge in the CDM pulse as a function of CDUT

The joint JEDEC/ESDA standard for CDM, JS-002  specifies four waveform parameters that must be met to qualify a FICDM tester, peak current, rise time, full width at half maximum and undershoot. We will not look at simulations of each of these parameters and see how they behave as a function of DUT capacitance. The parameters will also be compared to the waveform specifications from JS-002. In all cases the simulations fall within the experimentally determined waveform parameters in JS-002. This gives confidence that the simulations are a good representation of reality and are therefore useful for understanding the CDM event in FICDM testing

Figure 6 through Figure 9 show simulations of peak current, rise time, full width at half maximum and undershoot as a function of CDUT. In each of the figures the insert shows the behavior for low capacitance with a linear CDUT scale, while the main figure uses a log scale for CDUT for all capacitances simulated. All of the parameters show very sensitive dependence on CDUT for small CDUT, but saturation for large values of CDUT. Figure 6 Simulated Peak Current as a function of CDUT. The vertical lines indicate the JS-002 specification limits. Figure 7 Simulated rise time as a function of CDUT. The vertical lines indicate the JS-002 specification limits. Figure 8 Simulated full width at half maximum as a function of CDUT. The vertical lines indicate the JS-002 specification limits. Figure 9 Simulated undershoot as a function of CDUT. The vertical lines indicate the JS-002 specification limits.

# 5 Summary

In this article the three-capacitor model for the field induced CDM ESD test method has been used to help understand the properties of the CDM test system. The model shows that during the CDM event currents that flow are the result of a redistribution of charge between the three capacitors in the CDM system. For small DUT to field plate capacitance, when CDUT is well below the capacitance CFG between the Field Plate and the Ground Plane, the currents are more sensitive to the value of CDUT. When CDUT approaches and becomes larger than CFG waveform properties become less sensitive to CDUT. The general trends as CDUT gets larger is that peak current increases, rise times get longer, width at half maximum increases and the amount of undershoot decreases.

 J. Montoya and T.  Maloney, “Unifying factory ESD measurements and component ESD stress testing”, 2005 Electrical Overstress/Electrostatic Discharge Symposium,: 2005

 B. Atwood, Y. Zhou, Dave Clarke, and T. Weyl, “Effect of large device capacitance on FICDM peak current”, 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007

 A. Wallash and L. Levit, “Electrical breakdown and ESD phenomena for devices with nanometer-to-micron gaps”, Proc. SPIE V4980, 2003, pp. 87-96.

 ANSI/ESDA/JEDEC JS-002-2018, “For Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM) – Device Level” 2018