In an earlier blog I discussed the benefits of HBM testing using a low parasitic two pin testing versus a matrix-based tester. In that blog I put off the big challenge of testing with a two-pin tester, setting up the pin combinations to use for HBM qualification testing. In this blog I will tackle that issue. This is a challenge because the widely used JS-001-2017  test standard often assumes a matrix-based tester. What will be shown is that to efficiently do HBM qualification testing of high pin count integrated circuits using a two-pin tester requires a good understanding of the IC to be tested as well as comprehensive knowledge of JS-001 and the various options available to reduce the number of necessary pin combinations.
If you are unfamiliar with HBM pin combinations it is recommended to review my earlier blog posts on HBM and HBM pin combinations at https://minotaurlabs.com/category/hbm-human-body-model/.
There are three ways to develop pin combinations for two pin HBM testing, each with a possible option to represent supply pin groups with a single pin.
- Stress all pin pair combinations
- Test all pins
- Take advantage single pin per supply pin group allowances for
- Supplies connected with a package plane
- Supplies connected with above passivation layer (APL) interconnect
- Follow the traditional Table 2B pin combinations
- Without using package plane and APL allowances
- Using package plane and APL allowances if applicable
- Use the options available in Table 2A in JS-001 to eliminate signal pin to non-associated power and eliminate most non-supply to non-supply stress
- Without using package plane and APL allowances
- Using package plane and APL allowances if applicable
All of the above options will be covered. As we discuss these options it will become apparent that the more knowledge the test engineer has about the device being tested, the more the number of unique stresses which need to be performed can be reduced.
As with all blogs in this series, this blog is intended to give insight into the HBM test method. There is no substitute for reading the original test method.
Note: In this blog I will often be referring to Table 2A and Table 2B in JS-001. Whenever Table 2A or Table 2B is referenced it is a reference to the JS-001 tables. When Table 1, Table 2, or Table 3 are referenced it is to the tables in this document.
2 Supplies connected by Package Planes or APL
Before discussing pin combinations, the special allowances for package planes and above passivation levels (APL) will be discussed, since these allowances apply to all three methods of developing pin combinations.
JS-001-2017 makes an allowance to represent a supply pin group as a single pin if the supply pin group is tied together by a package plane or an above passivation layer (APL) which connects any two pins in the group with a resistance less than 1 Ohm. A package plane is a metal layer in an IC package tying a number of pins together. An APL is a metal layer on the surface of the die, but above the passivation layer which is used to move the position of various IC connections to more convenient locations for packaging. An APL is often called a redistribution layer.
With the very low resistances of package planes and APL the HBM stress to an IC is really the same if the stress is applied in parallel to all of the pins or to any individual pin of the supply group. Use of the package plane or APL single pin allowance can result in considerable reductions in the number of required pin combinations regardless how pin combinations are being selected.
Note, in HBM testing ground and VSS pin groups are considered supply groups.
3 Stress All Pin Combinations
In this method every pin is stressed positive and negative against every other pin. Many ESD engineers feel that this is the purest form of HBM testing, since every possible current path is exercised. Others will point out that for higher pin devices this is not allowed, since Section 6.5 of JS-001-2017 states that “Integrated circuits with ten pin or less may be tested with all pin-pair combinations.” It is easy to interpret this statement that if you “may” test all pin combinations if the device is 10 pins or less, you “may not” test all pin combinations if the device has greater than 10 pins. It is my understanding that prohibiting all pin combinations was not the intent and there is likely that this will be clarified in the next release of JS-001. For the rest of this discussion, we will assume that stressing all pin combinations is in fact allowed for all pin count devices.
The challenge of doing all pin combinations is that the number of pin combinations increases rapidly with increasing numbers of pins. Equation 1 calculates the number of unique pin pair combination for an IC with M pins, assuming a low parasitic HBM tester.
Equation 1 takes advantage of the allowance in JS-001 for low parasitic testers that you don’t have to stress pin B versus pin A if pin A versus pin B has been stressed both positive and negative.
Figure 1 shows the number of pin combinations as a function of number of pins if all pin pair combinations are performed. It quickly becomes clear that doing all pin pair combinations for a high pin count integrated circuit (IC) is not reasonable. For low pin count devices stressing all possible pin pair combinations can be a good choice. Assuming 5 seconds to stress a single pin combination positive and negative a 40 pin device could be tested in 65 minutes. While this amount of test time is not short, there is no engineering time expended determining if pins are supply pins, non-supply pins or determining supply pin groupings.
Figure 1 Number of pin combinations for stressing all pin pairs as a function of the number of pins.
4 Table 2B
JS-001 Table 2B, shown as Table 1 of this blog, is the traditional pin combinations which JS-001 inherited from the legacy JEDEC and ESDA HBM specifications. This method assumes a method of tying a number of pins together, which is most easily accomplished using a matrix based HBM tester. Table 2B includes two types of pin combinations. In combinations 1 through N all pins from a supply pin group are shorted on Terminal B and all pins not on terminal B are stressed, one pin at a time, versus the pins on Terminal B. This is then repeated for each supply pin group. In the second type of pin combinations, N+1, each non-supply pin is stressed versus all other non-supply pins tied together on Terminal B. This is then repeated for each non-supply pin.
Table 1 Reproduction of JS-001-2017 Table 2B. Notes have been left out.
Performing pin combinations 1 through N+1 on a two pin tester results in a very large number of pin combinations since there is no mechanism for tying Terminal B pins together on a two-pin tester. Each Terminal A pin needs to be stressed to each pin of each supply pin group connected to Terminal B. Considerable relief can be obtained if the pins of each supply pin group are tied together by package planes or APL as will be shown in Section 6.
When performing the N+1 pin combination set on a matrix-based tester there is one pin combination for each non-supply pin. With a two-pin tester it is necessary to stress each non-supply pin to every other non-supply pin individually. In this case the number of pin combinations in pin combination set N+1 is governed by Equation 1 above, where the number of pins, M, would be the number of non-supply pins.
As will be seen in Section 6 it is often unrealistic to perform full HBM qualification testing using a two-pin tester using the traditional Table 2B.
5 Table 2A
JS-001 Table 2A, shown in Table 2 of this blog, is a more viable option for higher pin count HBM qualification testing using a two-pin tester. Table 2A was first introduced in JS-001-2011 with the goal of reducing test time and reducing failures due to wear out when individual circuit elements were stressed hundreds or thousands of times during HBM testing.
Table 2 Reproduction of JS-001-2017 Table 2A. Notes have been left out.
There are two major changes in Table 2A from Table 2B. One involves the combination sets 1 through N and the second involves combination set N+1.
In both Tables 2A and 2B each supply pin group is tied to Terminal B while pins not in that supply pin group are stressed on Terminal A. In the traditional Table 2B ALL pins not in the Terminal B group are stressed. In Table 2A all supply pins not in the Terminal B group are stressed on Terminal A, but only non-supply pins “associated” with the supply group on Terminal B are stressed. Non-supply pins are associated with a supply if one of two conditions are met:
- Power for the non-supply pin’s operation is supplied by the supply pin group
- “A parasitic path exists between non-supply and supply pin group” (This covers pins such as open drain, high voltage tolerant, buffers which have a supply providing voltage to an N-well guard ring.)
For ICs with a large number of supply pin groups this can be a significant difference as we will see in the example in Section 6.
In Table 2A Combination Set N+1 there is no longer the requirement to stress each non-supply pin versus every other non-supply pin tied together. This is replaced by a requirement to stress only between “coupled non-supply pin pairs”. A coupled non-supply pin pair is a pair that “may have a potential ESD current path that does not involve supply rails.” The most common example of a coupled non-supply pin pair is a differential input/output pair. If an IC has no coupled non-supply pin pairs there are no pin combinations in set N+1. If there are coupled non-supply pairs there is just one pin combination for each coupled pair. This change significantly reduces the number of pin combinations for ICs with a large number of non-supply pins.
6 Comparing the Methods
To understand how the different methods of setting pin combinations compare we will consider a specific IC example.
- Number of pins: 400
- Number of supply pin groups: 8
- Pins per supply pin group: 18
- VSS groups: 4
- VDD groups: 4
- Number of non-supply pins: 256 = 400 – (8*18)
- Number of non-supply pins associated with each supply group: 64
- In most instances each non-supply pin is associated with two supply pin groups, a VSS group and a VDD group
- Number of non-supply pins which are members of coupled pairs: 128 (64 differential IOs)
Table 3 lists the number of pin combinations for each of the pin combination options discussed.
Table 3 Pin combinations necessary to test a 400 pin IC with 8 supply pin groups, 4 VDD groups and 4 VSS groups, with 18 pins per supply pin group. Each non-supply pin is associated with one VDD and one VSS supply group. Half of the non-supply pins are in differential pairs.
If all pin pair combinations are performed there are 79,800 pin combinations. This figure is obtained from Equation 1. If each supply pin group can be represented by a single pin the number of combinations drops to 34,716, as the IC becomes effectively a 264-pin device.
If Table 2B is used and supply pin groups cannot be represented by a single pin there are 78,576 combinations. This is not much of an improvement over doing all pin pairs. The only reduction in pin combinations is that stress between pins in the same supply pin are no longer required.
For Table 2B there is over a factor of two improvement if each supply pin group can be represented by a single pin if the pins are tied together by package planes or APLs. Note that with supply groups represented by a single pin testing all pin pairs and using Table 2B are identical tests. If we assume 5 seconds per pin combination to perform positive and negative stress, 34,716 pin combinations will take over 48 hours for a single device. This level of test time is doable, but is certainly not ideal.
Using Table 2A in a situation where supply pin groups cannot be represented by a single pin yields 13,744 pin combinations. Using the same 5 seconds per pin combination results in a test time of just over 19 hours.
If it is permitted to represent each supply pin domain by a single pin the number of pin combinations drops to a very manageable 604. At 5 seconds per pin combination the test time is just 50 minutes, a very reasonable test time for a single device.
As discussed in a previous blog, testing with a 2 pin, low parasitic HBM tester has considerable advantages in terms of waveform integrity, ability to monitor waveforms and simplicity of current paths during HBM stress. This blog has shown, however, that unless there is a good understanding of the IC being tested and the various options available in JS-001-2017 to reduce the necessary pin combinations test times on a two-pin tester can be unreasonably long and device wear out could become an issue. This is especially true for high pin count ICs with a large number of supply groups.
It is important to remember, that even if the number of pin combinations becomes too large to allow a two-pin tester to be used for HBM qualification, the two-pin tester remains unparalleled for diagnostics.
 “For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) – Component Level”, ANSI/ESDA/JEDEC JS-001-2017.