Commercial versus Automotive ESD Integrated Circuit Qualification

1 Introduction

This post will be discussing the differences between the ESD qualification requirements for integrated circuits intended for standard commercial applications and for automotive applications. Automobiles have always had electrical circuits. Even before electric headlights and electric starters, magnetos provided electrical pulses to power spark plugs. The amount of electrical circuitry increased steadily over the years, and today the radio was replaced long ago as the most sophisticated piece of electronics in a vehicle. The rapid expansion in the high-tech electronic content in the automobiles has attracted increased interest across a much wider section of the electronics industry than it has in the past. Integrated circuit suppliers wishing to become suppliers to the automotive industry must become familiar with the qualification requirements for automotive electronics.

The working environment for automotive electronics is much more severe than is common for most consumer applications. Automotive electronics must work in the dead of winter in Minnesota and crossing Death Valley in the summer. The automotive environment is also an electrically noisy environment, with wiring harnesses carrying sensing circuits as well as high current pulses to operate a wide range of motors and accessories. Automotive electronics are also often safety critical. It is therefore not surprising that the automotive industry has their own set of qualification requirements for electronic components.

Note: In this post I am trying to summarize the differences between ESD qualification for commercial and automotive integrated circuits. This summary should not be used as a substitute for a thorough reading of the full standards.

2 Qualification Documents

The qualification requirements for most commercial integrated circuits are dictated by JEDEC’s JESD47 “Stress-Test-Driven Qualification of Integrated Circuits” [1], while automotive integrated circuits are specified by the AEC (Automotive Electronics Council) Q100 standard, “Failure Mechanism Based Stress Test Qualification for Integrated Circuits” [2]. These two documents are very similar in their purpose and methodology. The two documents include the following types of requirements.

  • A list of stress tests required for qualification such as:
    • High Temperature Operation Life
    • Early Life Failure Rate
    • Temperature Humidity Bias
    • Human Body Model (HBM)
    • Charged Device Model (CDM)
  • Specification of the test method to be used for each test
    • JEDEC: mostly JEDEC tests, but some Military
    • AEC: a combination of AEC specific tests, as well as JEDEC and Military tests
  • Specification of requirements for each test such as:
    • Temperature for test
    • Humidity during test
    • Sample size
    • Number of failed samples allowed
    • Failure criteria
  • When each of the tests are required such as:
    • Design change
    • Change of gate oxide
    • Change of metallization
    • New fabrication site
    • …..

3 ESD Requirements

We can now compare the requirements for ESD testing in the JEDEC and AEC qualification documents. To do this the table entries for HBM and CDM in the two documents will be reproduced here, eliminating two columns from the AEC table which are not relevant to the current discussion.


Table 1 JEDEC requirements for HBM and CDM in JESD47K


Table 2 AEC requirements for HBM and CDM in Q100H

There are three notable differences between the qualification requirements in the two methods.

  • The test standards differ between JEDEC and AEC for both HBM and CDM
  • The requirements differ
    • JEDEC requires “Classification”
    • AEC gives specific target levels for both HBM and CDM
  • JEDEC requires 3 samples, while AEC says “See Test Method”

The difference in the test standards is not as stark as it seems. At the beginning of the AEC Q100-002 for HBM and Q100-011 for CDM are the following statements respectively.

All HBM testing performed on Integrated Circuit Devices to be AEC Q100 qualified shall be compliant to the latest revision of the ANSI/ESDA/JEDEC JS-001 specification, with additional requirements as defined herein.

All CDM ESD testing performed on Integrated Circuit devices to be AEC Q100 qualified shall be per the latest version of the ANSI/ESDA/JEDEC JS-002 specification with the following clarifications and requirements.

These statements show that the basic tests for HBM and CDM are essentially the same between JEDEC and AEC. The number of samples required is also the same. While JESD47 specifies three samples, JS-001 also specifies three samples. Q100-002 for HBM does not specify the number of samples, so the AEC requirement is governed by the three samples required by JS-001. For CDM, Q100-011 specifies three samples.

The difference in requirements is more substantial. JEDEC lists the requirements as “Classification”. The requirement is therefore that all integrated circuit designs must be tested for both HBM and CDM. The actual requirement is set by agreement between the manufacturer of the integrated circuit and the purchaser. For many years it was “common knowledge” that the specification for HBM was 2000 V and that that requirement was being reduced to 1000 V due to the activity of the Industry Council on ESD Targets. This “common knowledge” was in fact never true, for commercial product the ESD levels for both HBM and CDM have always been an agreement between supplier and purchaser.

AEC is much stricter in terms of requirements for HBM and CDM. The basic benchmarks for AEC ESD are an HBM passing level of 2000 V and a CMD passing level of 750 V for corner pins and 500 V for all other pins. As can be seen in Table 2, there are exceptions. Lower levels of ESD robustness can be accepted by the user. The note to see Section 1.3.1 is a requirement for reporting which reads:

For ESD, it is highly recommended that the passing voltage be specified in the supplier datasheet with a footnote on any pin exceptions. This will allow suppliers to state, e.g., “AEC-Q100 qualified to ESD Classification 2”.

Most of the remaining differences between the JEDEC and AEC ESD requirements are in the additional requirement in Q100-002 for HBM and Q100-011 for CDM.

3.1 HBM

This section will summarize the additional requirements for HBM testing according to Q100-002.

3.1.1 Waveform Requirements (Q100-002 Section 1.1)

This requires that all the tester meeting the waveform requirements at all test levels. (Legacy wording in JS-001 could be interpreted that the tester didn’t need to meet all waveform requirements, but this was never the intension.)

3.1.2 Test Fixture Board Qualification (Q100-002 Section 2)

Requires test fixture board meet waveform requirements at all test voltages, not limited voltages. Also specifies requalification if the board is repaired.

3.1.3 Device Stressing (Q100-002 Section 3)

Requires that device stressing be done at 500 V, 1000 V and 2000 V. Levels may not be skipped. JS-001 allows testing at a single level to establish the immunity level.  Q100-002 also specifies that if the device fails 500 V, it requires testing at 250 V, and if that fails testing at 125 V if the tester can meet the waveforms.

3.1.4 Devices with 6 pins or less (Q100-002 Section 4.1)

Devices with 6 pins or less must be tested with all pin pair combinations. (One pin on Terminal A and one pin on Terminal B.) JS-001 requires that discrete devices be tested with all pin combinations and allows devices with 10 or less pins to be tested with all pin pair combinations.

3.1.5 Pin Combination Table (Q100-002 Section 4.2)

JS-001 includes two options for pin combinations. Table 2B is the traditional pin combinations from the original version of JS-001 and is the same set of pin combinations as in the now obsolete HBM standards from JEDEC and ESDA. Table 2A is a new table which reduces the number of stresses on an integrated circuit, but requires more understanding of the device under test. The purpose of Table 2A is to reduce test time and, possibly more important, to reduce failures due to wear out.  Q100-002 requires all testing to start using Table 2B.

Q100-002 requires the use of Table 2B, but does give three options in which Table 2A may be used.

  • A low parasitic tester is being used
  • If a failure using Table 2B is deemed to be a false failure
  • If the use of Table 2B leads to failures due to wear out due to cumulative stress

3.1.6 Low Parasitic Tester (Q100-002 Section 4.3)

Q100-002 has special instructions if using a low parasitic tester such as a two-pin tester.

  • Connectivity must be verified for each stress
  • Non-supply to non-supply stress may be done using Table 2A
  • All adjacent non-supply pins must be stressed versus each other
  • The options in JS-001 Section 6.6 for low parasitic HBM testers may be used.

3.1.7 Reporting (Q100-002 Section 5.0)

Q100-002 has a section on reporting, which is lacking in JS-001. In addition to reporting the basic test results the reporting section requires information on the type of tester used, details on the samples and test details such as pin groupings, stress voltage levels, any portioning of stress over multiple devices, stress pin combinations, and any exceptions for the tests performed.

3.2 CDM

This section will describe the additional testing requirements for CDM testing according to Q100-011

3.2.1 Stress Levels Tested (Q100-011 Sections 2.3 and 2.5)

250 V is a required test level, and if higher withstand levels are to be reported testing has to be done in 250 V increments up to the highest passing level. It is not permissible to skip stress levels. If a device fails at 250 V testing is to be done at 125 V and if failure occurs at that level lower levels such as 100 V and 50 V are to be used. JS-002 allows testing at a single voltage and if all requirements are met that level can be used as the devices CDM withstand level.

3.2.2 Discharge Requirements (Q100-011 Section 2.5)

One of the most significant differences between JS-002 and Q100-011 is the number of zaps to each pin per voltage and polarity. Q100-011 requires 3 stresses on each pin for each voltage and polarity, while JS-002 requires “at least 1 discharge” per voltage and polarity. The wording of “at least 1 discharge” was added to JS-002 so that a single set of testing could cover both JS-002 and AEC Q100-11 testing.

3.2.3 Corner Pin Classification (Q100-11 Sections 1.3.1 & 2.6)

A unique feature of the AEC CDM is the corner pin requirement. As discussed in Section 2 the standard qualification level for CDM is 500 V, with corner pins at 750 V. Section 1.3.1 of AEC Q100-11 describes the definition of a corner pin, while Section 2.7 describes two methods to determine the 750 V corner pin classification.

3.2.4 Small Package Considerations (Q100-11 Section 2.7)

This section of Q100-11 discusses the difficulties of CDM testing of small package, and notes that in some cases it the testing may need to be skipped, but this must be noted and done in agreement with the user. This section came out before JS-002 included provisions to eliminate further CDM testing of small devices within a technology family with a known CDM history of robustness.

3.2.5 Wafer or Bare Die Considerations (Q100-11 Section 2.8)

This section discusses CDM testing of products shipped at wafer level or as bare die. The document allows bare die product to be tested in a surrogate package, as long as the package used is documented.

3.2.6 Failure Criteria (Q100-11 Section 2.9)

This section defines failure as not meeting all device specifications. The section also notes that after CDM testing device parameters can drift from out of specification back into specification. This section encourages post stress testing to be done soon after stress, but does not give a time limit.

3.2.7Acceptance Criteria (Q100-11 Section 2.10)

This section requires that to pass a specified classification level the device must also pass all lower test levels.

There are also some slight differences in the classification levels between JS-002 and Q100-11. To account for the 750 V corner pin requirement, AEC has inserted an extra level into their classification scheme, creating some confusion. The new Q100-11 level of C2 has the same definition as the JS-002 definition as JS-002 level C2a. To obtain the C2a level in Q100-11 requires corner pins passing 750 V or higher.

Table 3 Comparisons of JS-002 and Q100-11 qualification levels

4 Summary

In summary, the ESD requirements for commercial versus automotive qualification are very similar. Both require HBM and CDM testing based on the same two test standards, JS-001 for HBM and JS-002 for CDM. Automotive qualification has additional requirements, including specified qualification target levels, 3 versus 1 zap for CDM, and a number of additional requirements. The good news is that if a product has met the requirements of AEC Q100 for ESD qualification, the product will more than met the requirements for JEDEC/ESDA qualification for ESD.

5 References

[1] JESD47, “Stress-Test-Driven Qualification of Integrated Circuits”, JEDEC Solid State Technology Association,

[2] AEC – Q100 – Rev-H, “Failure Mechanism Based Stress Test Qualification for Integrated Circuits” Automotive Electronics Council,

[3] ANSI/ESDA/JEDEC JS-001-2017, “For Electrostatic Discharge Sensitivity Testing, Human Body Model (HBM) – Component Level”, EOS/ESD Association,,  and JEDEC Solid State Technology Association,

[4] ANSI/ESDA/JEDEC JS-002-2018, “For Electrostatic Discharge Sensitivity Testing, Charged Device Model (CDM) – Device Level”, EOS/ESD Association,,  and JEDEC Solid State Technology Association,

[5] AEC–Q100-002 REV-E, “Human Body Model Electrostatic Discharge Test”, Automotive Electronics Council,

[6] AEC-Q100-011 Rev-D, “Charged Device Model (CDM) Electostatic Discharge (ESD) Test”, Automotive Electronics Council,

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