Minotaur Labs ESD Design & Debug Services
When ESD failures occur during qualification testing it is imperative to determine the cause of the failure rapidly, and accurately. Physical failure analysis is often the first line of attack, but it is not the only tool available. Working with an experienced ESD test engineer to isolate the cause of the failure can also be very helpful. There are a number of tests which can help isolate the problem. We will review some of the measurement possibilities below. Minotaur Labs is also partnering with SRF Technologies (www.srftechnologies.com) to provide ESD Design support in addition to measurement Debug services when requested by customers.
During HBM testing on both the Grund system with two pin testing and on the ThermoFisher Mk2 Curve Trace, or current versus voltage testing, can be performed before and after each stress. This can give the earliest indication of failure on a specific stress condition. Examination of curve trace results is also useful when a failure is found during functional testing on automated test equipment (ATE) after HBM testing. Minotaur Labs engineers can help you understand curve trace data and how the measurement is done.
Caution is needed when using curve trace, valuable as it is. The ultimate test of failure is full functional test on ATE. There can be false failures, since the HBM pulse itself may actually place some transistors in a temporary on state or charge trapping may result in a temporary increased leakage. It is also possible for an integrated circuit be damaged, but not have the damage visible during curve trace.
Wear Out Issues
On very high pin count integrated circuits (ICs) can experience failure due to wear out during HBM testing as shared elements in the ESD protection circuitry are stressed dozens, or even hundreds of times during HBM testing. The HBM test is intended to evaluate how well an electronic component will survive in a manufacturing environment which has at least basic ESD control practices in place. In such an environment an integrated circuit should be exposed to a very limited number of ESD stresses of low intensity. The integrated circuit should never experience dozens of stresses during manufacture.
There are several methods which can address failures due to wear out. The pin combination Table 2B in JS-002 is the traditional set of pin combinations and is the easiest way to implement HBM testing. It does tend to stress some circuit elements repeatedly, dozens or hundreds of times. If a failure occurs with Table 2 pin combinations, Table 2A can be used. Greater knowledge is needed to set up Table 2A testing, since signal pins are only stressed versus power supplies that supply power to the signal pin being tested. For ICs with many power domains this can greatly reduce the number of stresses applied.
An alternate, or additional step which can be taken is to divide the testing between several different test samples. That is, rather than doing all pin combinations on a single device, the stresses are spread over several devices.
The Grund two pin test system has the unique ability to measure the voltage across the DUT during each HBM stress. Analysis of this voltage can help determine if the protection strategy is working as expected.
Special Pin Combinations
If specific pin combinations are suspected of causing issues Minotaur Labs can design custom pin combinations to isolate issues.
Matrix based HBM test systems such as the ThermoFisher MK2 have allowed very fast and efficient HBM testing. The presence of parasitic circuit elements in the matrix has, however, created a number of specialized conditions which have created false failures due to distortion of the HBM waveform. The Grund two pin tester eliminates those parasitic elements and can often be used to discount false failures.
Transmission Line Pulse (TLP)
TLP is a technique for applying square stress pulses to a device under test, while measuring the current through the device and the voltage across the device. This can be used to extract current versus voltage measurements as well as time dependent behavior of ESD protection strategies and the circuits they are protecting. TLP is the most popular electrical diagnostic took used by ESD specialists. TLP measurements performed by Minotaur Labs can provide insight into both successful and unsuccessful designs.
For more information on ESD Debug, Design and Analysis, contact your Minotaur Labs representative.