This blog post is an update of an article originally published in 2008 in the now defunct Conformity magazine. The original article is available elsewhere on the Minotaur Labs web site, but changes in the test standards for electrostatic discharge (ESD) have changed sufficiently to warrant a “freshening” of the article. Since that time Machine Model (MM) has largely been dropped as a test method and the JEDEC and Electrostatic Discharge Association (ESDA) CDM test standards have been merged into one standard and the Automotive Electronics Council (AEC) CDM standard now references the joint JEDEC/ESDA CDM standard rather than the old ESDA standard.
Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.
All ESD events consist of a charged object discharging through a discharge path. Characterizing an ESD event requires understanding both the capacitance and the discharge path. HBM can be described with the simple circuit diagram in Figure 1. This procedure works well because this test standard emulates a person becoming charged and discharging through the sample being tested. The capacitance of a person is approximately 100 pF and the discharge path for a human includes skin and body resistance, which is approximated by a 1500 Ω resistor. CDM is different. CDM emulates an integrated circuit that becomes charged during handling and discharges to a grounded metallic surface. The capacitance is the capacitance of the integrated circuit to its surroundings and the discharge path is a pin of the IC directly to a grounded surface. The test method for CDM must have a capacitance that scales with the device under test’s (DUT) capacitance and a discharge path with very little impedance other than the DUT’s own pin impedance and the resistance of the resulting arc. In CDM the stress is dominated by the properties of the device being tested, while in HBM the stress is dominated by the source of the stress, a charged person. The field induced CDM test setup is designed to allow the properties of the DUT to dominate the stress.
Figure 1 Basic circuit diagram used to describe HBM and MM
CDM Test Equipment
Figure 2 shows a representation of an FCDM simulator. The simulator consists of a metallic field plate covered with a thin layer of FR4 or similar circuit board material. The potential of the field plate can be controlled with a high voltage power supply through a high value resistor. Suspended above the field plate is a ground plane. At the center of the ground plane is a spring loaded pogo pin. The pogo pin is connected to the ground plane with a low inductance 1 Ω resistance to provide a current sense element. The pogo pin and ground plane are also connected to a 50 Ω coaxial cable. The separation between the field plate and the ground plane as well as the relative position of the ground plane over the field plate is computer controlled.
Figure 2 Field Induced Charged Device Model Simulator
Placing the DUT with the pin side up (dead bug position) produces a capacitance between the DUT and the field plate that scales with the size of the DUT. A low inductance discharge path to ground is formed by moving the ground plane relative to the field plate such that the pogo pin can touch any pin on the DUT. The 1 Ω resistor and coaxial cable provide a low inductance current sensor so that discharge waveforms can be conveniently measured. The process of “charging” and “discharging” the DUT is where most of the confusion over FCDM occurs. Confusion about the test procedure is understandable because the actual process is opposite from what is expected. It is often stated that in FCDM the DUT is inductively charged and then discharged by contacting the pogo pin to the DUT. In fact, field induction does not place any charge on the device. Also, the “discharge” when the pogo pin first touches the DUT is when the DUT is actually charged.
Figure 3 Capacitors added to field induced CDM simulator
In Figure 3 a circuit diagram is overlaid on top of a simplified version of the FCDM simulator. This circuit is a simplification of the full circuit but shows the most important features. A very thorough theoretical treatment of FCDM testing is provided by Atwood et. al. CDF is the capacitance of the DUT to the field plate, CDG is the capacitance of the DUT to the ground plane and CFG is the capacitance of the field plate to the ground plane. Touching the pogo pin to a pin on the DUT has been represented by the switch S. Key to the understanding of FCDM is the series capacitors CDUT and CDG. Assuming no initial charge on the DUT, with the switch S open the DC voltage between the DUT and the Field Plate is:
Because the separation of the DUT from the field plate is always much less than the separation of the DUT from the ground plane; CDF is always much larger than CDG. The voltage between the DUT and the field plate, VDF, will be small and the DUT potential will therefore closely track the power supply voltage. The potential of the DUT relative to the ground plane can therefore be controlled without actually putting any net charge on the DUT.
CDM Test Sequence
There are two procedures for doing FCDM stressing. A positive and a negative stress can be performed with a single charging of the field plate or positive and negative stresses can be done separately. The two procedures start out the same. The single stress method will be described first, followed by the dual polarity stress.
- With the field plate at zero volts an uncharged DUT is placed on the field plate in the dead bug position and the ground plane is positioned with the pogo pin above the pin to be tested.
- The field plate is raised to a high potential, for example +500 V. The high value resistor ensures that the field plate changes potential relatively slowly. The slow change in potential ensures that the DUT is not damaged before the CDM event. The potential of the DUT will closely track the field plate, reaching in excess of 450 V, although there will be no net charge on the DUT.
- After the voltage has stabilized the separation between the field plate and the ground plane is reduced until an arc forms between the pogo pin and the DUT pin and eventually the two pins touch. This is equivalent to closing the switch S in Figure 3.
- Closing S in the circuit diagram produces a very rapid grounding of the DUT and a redistribution of charge between the three capacitors. Only the 1 Ω resistor, arc resistance and the inductance of the pogo pin, arc and the DUT pin limit the current pulse. The peak current can be anywhere from a fraction of an Amp to 20 A depending on the size of the DUT. At this point the DUT is charged and the potential between the field plate and the ground plane has fallen as the capacitor CFG provides charge to the DUT. During this redistribution of charge, which usually lasts under 2 ns, the high voltage power supply and the high value resistor can be ignored because of their slow response time.
- After the initial redistribution of charge the field plate will slowly return to the voltage on the high voltage power supply, while the DUT remains at zero potential, but in a charged state.
At this point the single pulse and dual pulse procedures begin to differ. We will continue with the single pulse procedure.
- With the pogo pin still touching the DUT pin the HV power supply voltage is set to zero. The field plate will slowly return to zero volts and the charge on the DUT will slowly bleed off through the pogo pin.
- When the field plate is at zero volts the distance between the field plate and ground plane can be returned to the original separation. At this point the procedure can be repeated for another stress on the same pin, a stress on the same pin with opposite polarity, or testing can be continued on a different DUT pin.
A sample FCDM waveform for a small JEDEC calibration module is shown in Figure 4. The waveform shows the typical CDM characteristic; a very high current short duration pulse.
Figure 4 Field Induced CDM waveform of a small JEDEC Module at 500 V
The dual pulse procedure continues after step 5 of the single polarity procedure.
- Without changing the voltage on the HV power supply the distance between the field plate and the ground plane is increased so that the pogo pin separates from the DUT pin. The DUT is still charged and will stay at approximately zero volts while the field plate is at the HV power supply voltage.
- The potential on the field plate voltage is slowly returned to zero by setting the HV supply to 0 V. Changing the field plate potential to zero volts does not change the fact that there is a nearly 500 V potential across the capacitor CDF. The result is that when the field plate reaches zero volts, the DUT potential is close to -500 V.
- At this point the separation of the field plate and ground plane is decreased until an arc forms between the pogo pin and the DUT pin, rapidly grounding the DUT. This results in a second stress pulse with approximately equal amplitude as the first, but opposite polarity.
- After a suitable delay, to allow the field plate to return to zero volts after the arc, the separation between the field plate and the ground plane is increased and the test sequence is complete. Further stresses can be performed on the same pin or testing can be continued on other DUT pins.
The dual pulse method can save some time during FCDM testing.
The joint JEDEC/ESDA standard JS-002-2018 is the most widely used CDM test method. The Automotive Electronics Council (AEC) Q100-011 test method is based on the JS-002 standard, but has several additional requirements for automotive applications. The IEC CDM standard, IEC 60749-28 Ed.1, is mostly a copy of the JS-002 CDM standard. (IEC 60749-28 Ed.1 also includes an Annex which describes a direct, rather than field induced, charging method which follows the Japanese, JEITA EIAJ ED-4701/300 Test Method 305. This test method does not necessarily produce the same results as the field induced CDM method of JS-002.)
FCDM is an extremely valuable test method for ensuring that integrated circuits can survive in a modern, automated manufacturing environment. The test method creates a capacitance that scales with DUT size and a low impedance discharge path, providing a good simulation of real CDM events.
 ANSI/ESDA/JEDEC JS-002-2018 “For Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM) – Device Level.
 B.C. Atwood, Y. Zhou, D. Clarke, T Weyl, “Effect of Large Device Capacitance on FICDM Peak Current” EOS/ESD Symposium, 2007.