1 – Introduction
In a previous blog, HBM Basic Waveform, we discussed the circuit diagram and basic waveform for the Human Body Model (HBM) ESD stress test. That blog did not, however, address how the HBM waveform is applied to an integrated circuit. The device under test (DUT) was simply represented as a 2 pin device. One possibility would be to stress between all possible two pin combinations. This can lead to a very large number of stresses, even for low pin count devices. The number of pin combinations for a device with N pins can be written as:
This sequence builds rather quickly. For a 10 pin device there are 55 pin combinations, for 100 pins 5050 and for 1000 pins 499,500 combinations. These numbers must be doubled to allow for positive and negative stress. It was clear to the developers of the standard that a more economical choice of pin combinations was needed.
The origin of the pin combinations in the HBM standard is somewhat shrouded in mystery. One story I have heard is that during an early HBM standards meeting a design engineer stood up and drew a simplified circuit diagram of an integrated circuit and drew the possible current paths during an ESD event. The proposal was adopted and the design engineer has not been seen since and no one knows his name. The proposal worked well for many years, although recently some modifications have been made. In this blog post I will introduce the traditional HBM pin combinations which are in Table 2B of the Joint JEDEC/ESDA HBM standard JS-001 2017 . In a later blog I will address Table 2A with the newer pin combinations and the motivations for the updates as well as how testing can be done with a 2 pin tester.
2 – Traditional Pin Combinations
Table 1 is a reproduction of Table 2B in JS-001-2017 and is the traditional set of pin combinations which have been used for many years in the joint JEDEC/ESDA HBM standard JS-001 2017 and the separate JEDEC and ESDA HBM standards which proceeded JS-001. To understand the pin combinations, it is necessary to understand three terms, supply pin, supply pin group and non-supply pin. JS-001 goes into a great deal of detail on these terms, but in this blog we will focus on the basics needed for understanding pin combinations.
A supply pin is any integrated circuit pin used to provide power to the circuit. It is important to know that ground pins are considered power pins. Typical names for supply pins are, VDD, VDDA, VSS, VSSA, GND and as well as many variations on these names.
The power demands for many integrated circuits (IC) are large enough that a single pin cannot supply all of the current needed by the device without excessive voltage drops and power dissipation, either within the IC or in the connection of the IC to a printed circuit board. In these situations, from 2 to dozens of supply pins may be tied together with metal on the die of the IC or in the package. Supply pins tied together in this manner create a supply pin group. Note that even though two supply pins may have the same supply voltage they are not part of the same supply pin group unless they are metallically connected on the die or in the package. For example, a digital ground and an analog ground may both be tied to ground on a circuit board, but they are not part of the same supply pin group because they are likely isolated from each other on the die of the IC. We will see an example of this when we give examples in the next section. (JS-001 has additional requirements of low resistance between pins within a supply pin group as well as conditions in which a single pin can represent a supply pin group, but for simplicity we will not address those conditions here.)
|Pin Combination Set Number||Pin(s) Connected to Terminal B||Pin Connected to Terminal A|
(Single Pins, tested one at a time)
|1||Supply Pin Group 1||Every Supply Pin except pins of Supply Pin Group 1|
|Every Non-Supply Pin|
|2||Supply Pin Group 2||Every Supply Pin except pins of Supply Pin Group 2|
|Every Non-Supply Pin|
|N||Supply Pin Group N||Every Supply Pin except pins of Supply Pin Group 1|
|Every Non-Supply Pin|
|N + 1||All Non-supply Pins except Pin Under Test||Each Non-Supply Pin as Pin Under Test|
Table 1 Traditional JEDEC/ESDA pin combinations for HBM testing. This table is a copy of Table 2B in JS-001 2017
Once supply pins are understood it is easy to understand non-supply pins. Non-supply pins are simply all pins which are not supply pins or no connects. Non-supply pins are mostly inputs, outputs and input/output pins. No connect pins are package pins with no connection to the IC die. No connect pins are not tested during HBM and may be a topic for a future blog post.
Table 1 shows there to be N + 1 sets of pin combinations, where is N is the number of supply pin groups. In the n = 1 to N sets of pin combinations each of the supply pin groups are shorted together and connected to the B terminal of the HBM tester. (The B terminal of an HBM tester is the side closer to ground, while the A side is connected to the HBM pulse source. The B side of the HBM tester is not strictly ground since termination resistance is needed to suppress reflections.) While all pins of supply group n are connected to terminal B, each supply pin not part of supply pin group n is connected to terminal A, one at a time, and positive and negative HBM stress is applied from terminal A to terminal B. This is repeated for each of the N supply pin groups.
After all supply groups 1 to N have been connected to terminal B, non-supply to non-supply stress needs to be addressed. To reduce test time and number of stresses the early HBM standards groups elected not to stress each non-supply pin to every other non-supply pin individually. Instead each non-supply pin was connected to terminal A, one at a time, and stressed versus all other non-supply pins shorted together and connected to terminal B. This arrangement is not exactly realistic but does save considerable test time.
3 – HBM Stress of a Typical Circuit
In this section we will show how the pin combinations above test out the ESD protection on a popular style of ESD protection, which uses steering diodes on all inputs and outputs coupled with ESD protection circuits between all power supplies and their respective grounds. The VDD to VSS protection could be of the form of a dynamic clamp as presented in . Dynamic clamps prove protection during a positive transient on VDDn versus VSSn. For a negative stress protection is provided by the diode naturally present between VDDn and VSSn. This ESD protection strategy can provide a low impedance current path for ESD stress between any two pins on the integrated circuit. How this scheme works will become clear as we discuss pin combinations.
Figure 1 shows a simple schematic which we will use to represent a full integrated circuit. It includes two power supply domains (4 supply pin groups) VDD1-VSS1 and VDD2-VSS2 as well as Inputs and Outputs for each of the power domains. The two VSS busses are isolated from each other with a pair of anti-parallel diodes to create plus and minus diode drop of isolation between the grounds. Note that each VDD and VSS supply pin group may be represented by from 1 to dozens of individual package pins.
Figure 1 Representative schematic of an integrated circuit using power supply protection with steering diodes on all IOs
Figure 2 and Figure 3 illustrate positive and negative stress respectively on supplies VDD1, VDD2 and VSS1 on Terminal A versus VSS2 on Terminal B. For both the positive and negative stresses VSS1 to VSS2 the diodes between the two VSS lines provide a low impedance path between the supply domains. Positive stress to VDD pins uses the Supply Protection to provide the low impedance path during stress.
Figure 2 Positive stress from VDD1, VSS1 and VDD2 on Terminal A to VSS2 on Terminal B
During negative stress on VDD1 and VDD2 the diodes inherently present in the technology provide the low impedance paths from VDD to VSS.
Figure 3 Negative stress from VDD1, VSS1 and VDD2 on Terminal A to VSS2 on Terminal B
Figure 4 and Figure 5 illustrate the low impedance current paths for positive and negative stress of non-supply pins respectively. Note how the steering diodes “steer” the current to the VDD and VSS lines. Once the stress is directed to the VDD and VSS lines the current paths are similar to the paths used during stress of supply pins.
Figure 4 Positive Stress from non-supply pins on Terminal A to VSS2 on Terminal B
Figure 5 Negative Stress from non-supply pins on Terminal A to VSS2 on Terminal B
Pin Combinations N + 1 from Table 1 result in somewhat more complicated current paths for each stress, since all non-supply pins not connected to Terminal A are tied together in the tester to Terminal B. The possible current paths for the stress of I1 versus all other non-supply pins are shown in Figure 6 and Figure 7 for positive and negative stress respectively. If we follow the current paths for I1 to other non-supply pins in Figure 6 or Figure 7 we see that the current path that leads to the other non-supply pin in the VDD1-VSS1 power domain has one fewer forward bias diode drops than the current paths to the pins in supply domain VDD2-VSS2. It is therefore likely that most of the stress current will remain within the VDD1-VSS1 power domain.
Figure 6 Positive Stress on I1 on Terminal A versus all other non-supply on Terminal B
Figure 7 Negative Stress on I1 on Terminal A versus all other non-supply on Terminal B
4 – Summary
In this article we have discussed the traditional pin combinations that have been used during HBM testing for many years. A sample circuit was used to demonstrate how the traditional pin combinations exercised all of the necessary low impedance paths which must exist for proper protection of an integrated circuit from HBM stress. These pin combinations have served the electronics industry for many years and have prevented integrated circuits with poor HBM performance from entering the marketplace.
The traditional pin combination represented in Table 1 (Table 2B in JS-001-2017) are not without issues however. As the number of supply pin groups has increased over the years from 2 to dozens on large integrated circuits the number of pin combinations has increased dramatically. The result has been excessive test times and wear out of the integrated circuit as sections of the integrated circuit are tested up to thousands of times during HBM testing. In a future article we will address how Table 2A in JS-001 2017 can reduce stress time and wear out. In another future article we will discuss how two pin testing can be performed on high pin count circuits without excessive test times using the provisions in JS-001.
5 – References
- ANSI/ESDA/JEDEC JS-001-2017, “For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) – Component Level”
- Worley, Gupta, Jones, Kjar, Nguyen and Tennyson, “Sub-Micron Chip ESD Protection Schemes which Avoid Avalanche Breakdown”, EOS/ESD Symposium 1995.