Machine Model (MM) – Don’t Do It

1 – Introduction

Traditionally there have been three test methods for evaluating the robustness of integrated circuits to electrostatic discharge (ESD) damage during manufacturing, Human Body Model (HBM), Machine Model (MM) and Charged Device Model (MM). Recently MM has fallen out of favor and is no longer a requirement nor accepted test for qualification based on either the JEDEC’s JESD47I or the Automotive Electronics Council (AEC) Q100. Many OEMs, however, have a long history of requiring MM testing and are reluctant to give up on a test that they believe has served them well.  It is reasonable, in an era in which almost all manufacturing is done using automated equipment, that a test with the name Machine Model should be an important ESD test.

In this blog it will be shown that Machine Model does not represent the type of stress which occurs in a manufacturing line and the information that it provides is redundant to HBM.

2- Background

MM was originally developed in Japan, but the name Machine Model was not used by the original developers. [1] The original intention was to create a human body ESD test which did not require the high voltages required during HBM testing. The name Machine Model was given to it by others, probably in the United States. The assumption was, since there was no explicit resistor in the model the results would be similar to what would occur in a low resistance, metal to metal contact. The problem, is that the stress waveform produced by the MM test method does not represent the most important aspects of a metal to metal contact.

3 – Machine Model Specification

The MM equivalent circuit is usually represented as shown in Figure 1, a 200 pF capacitor discharging directly into the device under test (DUT) [2]. The ESDA MM test method [3] includes a 0.75 uH inductor and a 10 Ohm resistor in the schematic for reasons that will be clear when we look at the required waveforms. During waveform qualification and verification of the MM tester the DUT is replace by a short and a 500 Ohm load. Representative waveforms for those two cases are shown in Figure 2 and Figure 3 and the required waveform parameters in the JEDEC standard are shown in Table 1.

Figure 1 Circuit diagram often used to represent Machine Model. In the ESDA version the pulse source is represented only as a box with the text, 200 pF and 0.75 uH.

Figure 2 Required current waveform for a short from JEDEC MM standard (from JESD 22A115C)

Figure 3 Required current waveform through 500 ohm resistor from the JEDEC standard (from JESD 22A115C)


Voltage Level (V) Positive

Ipeak for Short, Ips1


Positive Ipeak for 500 Ohm*

Ipr (A)

Current at 100 ns for 500 Ohm, IR


Maximum Ringing Current, IR


Resonance Frequency for Short, FR (1/tfr)


100 1.5 – 2.0 N/A N/A Ips1 X 30% 11 – 16
200 2.8 – 3.8 N/A N/A Ips1 X 30% 11 – 16
400 5.8-8.0 I100 X 4.5


0.29 ± 20% Ips1 X 30% 11 – 16
* The 500 ohm load is used only during Equipment Qualification

Table 1 Waveform parameters from the JEDEC MM standard (from JESD 22A115C)


Even after a casual observation the waveforms do not look particularly like what would be expected from the circuit diagram in Figure 1 and the inductor and resistor included in the ESDA test method begin to make sense. The damped oscillation implies the required inductor and resistance. Using the equation for the resonant frequency of an inductor – capacitor circuit,

with 200 pF and 0.75 uH predicts a frequency of 13 MHz, near the middle of the frequency range in the JEDEC MM standard.

The large oscillations in the 500 Ohm waveform is not however predicted by either the JEDEC or ESDA schematics. A 200 pF capacitor discharging through a 0.75 uH inductor and 510 Ohms of resistance predicts a sub 10 ns rise time followed by an exponential decay with a 100 ns time constant. The large oscillations seen in Figure 3 would not be expected. It is therefore obvious that the traditional schematic shown in Figure 1 leaves out important circuit elements. A simple LTSpice simulation can give us a much better understanding of the true schematic of a MM simulator.

(Note, there is no requirement that the oscillations in the 500 Ohm waveform in Figure 3 be present. As will be shown below, they are caused by unavoidable parasitics in a realistic MM tester.)

4 – Simulations

Simulations of MM were performed using the schematic in Figure 4. This schematic includes the 0.75 uH inductance and 10 Ohms included in the ESDA test method. What is added is a lumped, 20 pF, parasitic capacitance between the inductor and ground. The results for 400 V are shown in Figure 5 for a short (0.1 Ohm) and Figure 6 for 500 Ohms. The results are similar to those in Figure 3 and Figure 4. The biggest difference is that the simulation shows a high frequency ring in the Short simulation. This high frequency ring is actually present in the sample Short waveform in the ESDA test method. The placement of Capacitor C2 determines if there is a high frequency ring in the short waveform. If C2 is placed directly across RDUT there is no high frequency ringing in the Short simulation, but the oscillation remains in the 500 Ohm simulation.

Figure 4 Schematic of LTSpice simulation of MM

Figure 5 Simulation of 400 V MM through a 0.1 Ohm resistor

Figure 6 Simulation of 400 V MM through a 500 Ohm resistor


5 MM versus Real Metal to Metal Contact

The best measurements of what a “real word” machine, metal to metal, contact were reported in 2003 at the EOS/ESD Symposium by Jon Barth and his co-authors. [4] They charged large metal frames to voltages up to 200 V and discharging them into a high bandwidth current measurement target. Sample results are shown in Figure 7. The results show a fast rise time initial pulse, followed by ringing with a frequency of about 63 MHz. The measured ringing, although at a higher frequency than the approximately 13 MHz of MM, shows at least some similarity to MM. The initial spike, which is a far more severe stress than the ringing which follows, is not represented in MM at all. The expanded time scale on the bottom of Figure 7 shows the rise time of the initial pulse to be on the order of 100 ps.

The rapid rise and magnitude of the initial current spike in the Barth measurements casts into question the validity of the MM test method as a predictor of ESD performance during real metal to metal ESD events. Simulations predict a 10 to 90 % rise time for MM testing of almost 12 ns. This is even longer than the 2 to 10 ns rise time allowed during HBM testing.

Figure 7 Figure 6 from Barth paper. Top figure is 20 ns per division and the bottom figure shows the initial current rise at 400 ps per division

The main feature of the real metal to metal contact, the initial current spike much more closely matches a Charged Device Model (CDM) test than the MM test. The question then remains, does MM provide additional information not covered in the Human Body Model test?

6 Does MM offer better information than HBM?

The Industry Council on ESD Target Levels studied this issue extensively. As reported in [1], HBM testing always provides a level of MM robustness. In all of the analysis that the Industry Council they found no field return data which indicated that a field return could be reproduced with MM that could not also be replicated by HBM. This is not true for CDM. Charged device model usually creates distinct failure mechanism from HBM and MM failure signatures. CDM failure signatures also more closely resemble the types of failures seen in a manufacturing environment than HBM and MM failure signatures.

7 Conclusions

It has been shown that the MM test method does not represent the real threat from a metal to metal contact due to the large inductance required to meet the waveform requirements. The fast rise time of a metal to metal contact is reproduced more accurately with the CDM test method. Additionally, MM is redundant with respect to HBM in terms of rise time, pulse duration and the failure modes detected. The performance of MM testing on integrated circuits is not a value-added test method and should not be used.

8 References

[1] Charvaka Duvvury, “Discontinuing Use of the Machine Model for Device ESD Qualification”, In Compliance Magazine, July 1, 2012. Available at:

[2] JEDEC JESD22-A115C, “Electrostatic Discharge (ESD) Sensitivity Testing, Machine Model (MM)”, November, 2010. (This document is no longer available on the JEDEC web site.)

[3] ANSI/ESD STM5.2-2012, “Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing – Machine Model (MM) – Component Level”, July 29, 2013.

[4] Jon Barth, John Richner, Leo G. Henry, and Mark Kelly, “Real HBM & MM – The dV/dt Threat”, 2003 EOS/ESD Symposium.

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