Parasitics in Matrix based HBM Testers

In a previous blog I discussed the basics of the Human Body Model (HBM) current waveform. The simplified circuit is shown in Figure 1. As discussed in the previous blog, for a low impedance device under test (DUT) this produces a fast-rising current pulse with an approximately 150 ns exponential decay time. Of course, real HBM test systems are much more complex than shown in Figure 1. For testing high pin count integrated circuits matrix based HBM test systems are often used. These systems provide a convenient automated testing of complex integrated circuits. Unfortunately, complex systems can have unexpected consequences. In this blog I will discuss how parasitics introduced by the relay matrix can have negative impact on the stress waveform, which can lead to false failures.

Figure 1Simplified HBM circuit diagram

Figure 2 shows a conceptual schematic of a matrix based HBM test system. A relay matrix allows any single pin to be connected to the HBM pulse source and one or more pins to be connected to ground. The matrix based HBM tester opened the way for fully automated HBM testing, allowing the many HBM pin combinations to be performed rapidly and with confidence. In 2004, however, a paper was presented by Texas Instruments (TI) [1] which showed that parasitics in the switch matrix could distort the stress applied to the DUT and lead to false failures. The ESDA HBM standards working group did further work to understand tester parasitics and published a paper in 2006 elaborating the issue [2].

Figure 2 Conceptual schematic of a matrix based HBM tester

Parasitic capacitance and inductance are present in all electronic systems. The HBM specification recognizes the presence of parasitics by having a fairly wide rise time specification as well as placing an upper limit on parasitic capacitance by requiring a 500 ohm qualification test which will expose extensive parasitic capacitance. The TI paper showed that when an integrated circuit (IC) is inserted into the tester’s socket the IC can interact with the tester to distort the waveforms the DUT sees. The problem is illustrated in Figure 3, where three channels of the HBM tester have been shorted together by the IC. The short is usually due to power supply domains which have multiple pins. The potential for shorting several pins together is straight forward when stressing one pin on a power supply domain with many pins. It can also happen when an I/O, which includes didoes to power and ground, is stressed. During the stress the diodes become forward biased, essentially connecting the stressed IO to a power supply domain. While these parallel capacitive current paths can’t carry a dc current, they can carry current during a transient. This will modify the current through the intended path in the IC.


Figure 3 Schematic of Matrix HBM tester showing how internal connections in an integrated circuit can tie tester channels together

This can be seen more clearly in the schematic in Figure 4. The schematic for the HBM pulse source is based on the schematic proposed by van Roozendaal and his coauthors in 1990 [3], and uses values of inductance and capacitance in parallel with the main HBM resistor based on value extracted by Verhaege and his coauthors [4]. The 6 uH inductor provides the slow, several ns, rise time for the HBM waveform, while the 1.5 pF capacitor results in the slight overshoot in the waveform which will be seen below. In the simulations the DUT resistance will be assumed to be zero because during an ESD event ESD protection elements in most ICs will have resistances of just a few ohms. This is much less than the 1500 ohm source resistance of the HBM pulse source.

One of the first questions that might be asked about the diagram in Figure 4 is why is there a 50 ohm resistor in the DUT channel of the tester? That doesn’t match the circuit diagram in Figure 1. The answer is that without some form of termination resistor on the ground side of the DUT there would be very large reflections in the system. Reference [2] found that the termination values on different matrix based tester varied from 50 to 100 ohms.

Figure 4 Schematic used in simulations

Before discussing the simulation results it is important to note that these simulations are for example only. They do not represent any specific tester, although the general trends match some of the measurements reported in [2]. It is also important also to note that the simulations are a lumped element model and may not accurately represent the distributed elements present in a real HBM test system.

Simulation of the current as measured at the HBM Source (I Source) is shown in Figure 5 with from no parallel parasitics to 32 channels of parasitics. The added parasitic elements result in extra ringing, but little change to the overall waveform. The situation changes dramatically if we look at the current measured through the DUT, as shown in Figure 6. The parallel channels create extensive ringing in the current through the DUT. The cause of this ringing can be seen more easily if we compare the HBM source current, DUT current and Parasitic path current for a particular number of parasitic channels. This is shown in Figure 7 for the case of 32 parallel parasitic paths.

Figure 5 Simulation of HBM Source Current with 0 to 32 parasitic channels in parallel to the DUT channel

Figure 6 Simulation of Current through the DUT with 0 to 32 parasitic channels in parallel to the DUT

It the beginning of the HBM pulse the capacitance of the parasitic path provides a lower impedance than the DUT in series with the termination resistor. Significant current doesn’t start to flow in the DUT until the parasitic capacitance becomes charged and the DUT becomes the preferred current path. With the capacitor charged the circuit loop consisting of the DUT, termination resistor, channel inductances and parasitic capacitor acts as a classic underdamped LCR resonant circuit.

Figure 7 The current in the HBM Pulse Source, through the DUT and in the Parasitic Channels for the case of 32 parallel parasitic channels

The important question is, how does this affect test results. A number of papers such as [1] have reported issues with false failures due to tester parasitics. Some protection design styles may not be sensitive to parasitcs, but dynamic circuits sensitive to stress rise times could be very sensitive.

What can be done to reduce the effects of tester parasitics? Thermo Fisher has introduced an ultra-low parasitic version of their Mk2 which reduces each channel’s capacitance by an order of magnitude. Another option is the two pin HBM system from Grund Technical Solutions which uses wafer probe needles to stress packaged devices with HBM. This virtually eliminates parasitics during HBM testing. I will discuss this type of testing in a future blog post.


[1] Kunz et al., “The Effect of High Pin-Count ESD Tester Parasitics on Transiently Triggered ESD Clamps”, EOS/ESD Symposium, 2004.

[2] Chaine et al., “HBM Tester Parasitic Effects on High Pin Count Devices with Multiple Power and Ground Pins”, EOS/ESD Symposium, 2006.

[3] van Roozendaal et al., “Standard ESD Testing of integrated Circuits,” EOS/ESD Symposium, 1990.

[4] Verhaege et al., Analysis of HBM ESD Testers and Specifications Usijng a 4th Order Lumped Element Model”, EOS/ESD Symposium, 1993.


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