ESD Publications

Publications by Robert Ashton on ESD


“Electrostatic Test Structures for Transmission Line Pulse and Human Body Model Testing at Wafer Level”, with S. Fairbanks, A. Burger, and E. Grund,  ICMTS 2018

“Extraction of time dependent data from time domain reflection transmission line pulse measurements [ESD protection design]”, ICMTS 2005.

“Transmission line pulse measurements: a tool for developing ESD robust integrated circuits”, ICMTS 2004

“Verification structures for transmission line pulse measurements for the study of ESD”, ICMTS 2002.

“Modified transmission line pulse system and transistor test structures for the study of ESD”, ICMTS 1995



“HMM single site testing: Can we reproduce component failure level with the HMM document?”, with Mirko Scholz, Theo Smedes, Richard Derikx, Marcel Dekker, Jon Barth, EOS/ESD 2016.

“JS-002 module and product CDM result comparison to JEDEC and ESDA CDM methods”, with A. Righter; B. Carn; M. Johnson; B. Reynolds; T. Smedes; S. Ward; H. Wolf, EOS/ESD 2016.

“Progress towards a joint ESDA/JEDEC CDM standard: Methods, experiments, and results”, with CDM joint working group, EOS/ESD 2012.

“HMM round robin study: What to expect when testing components to the IEC 61000-4-2 waveform”, with Kathleen Muhonen; Robert Ashton; Theo Smedes; Mirko Scholz; Rudolf Velghe; Jon Barth; Nathaniel Peachey; Wolfgang Stadler; Evan Grund, EOS/ESD 2012.

“FCDM measurements of small devices”, with M. Johnson & Scott Ward, EOS/ESD 2009.

“Characterization of Off Chip ESD Protection Devices”, with Lionel Lescourzeres, EOS/ESD 2008.

“VF-TLP Round Robin Study, Analysis and Results”, TLP working group, EOS/ESD Symposium 2008.  EOS/ESD 2008.

“HBM tester parasitic effects on high pin count devices with multiple power and ground pins”, with HBM working group. EOS/2006.

“Pre Pulse Voltage in the Human Body Model” with E. Worley, EOS/ESD 2006

“Voltages before and after current in HBM testers and real HBM”, with Jon Barth; Eugene Worley; John Richner, EOS/ESD Symposium 2005. EOS/ESD 2005.

“Voltages before and after HBM stress and their effect on dynamically triggered power supply clamps” with B. E. Weir; G. Weiss; T. Meuse, EOS/ESD 2004.

“Standardization of the Transmission Line Pulse (TLP) Methodology for Electrostatic Discharge (ESD)”, ESDA TLP Working Group. EOS/ESD Symposium 2003.

Characterization of a 0.16m CMOS Technology using SEMATECH ESD Benchmarking Structures”, with Yehuda Smooha, EOS/ESD Symposium 2001.



“Field Induced Charged Device Model: What really happens”, date of publication unknown. Conformity – FI-CDM What Really Happens

“The Futuire of ESD Testing”, date of publication unknown but dates from October 2008. Conformity – Future of ESD Testing

Title: “Challenges in Testing”, Subtitle: “Human Body Model (HBM): The Hidden Challenges” Publication date unknown but dates from May, 2008. Conformity – HBM Issues

“ESD Open Forum: HMM” This is from an ESDA section of Conformity and is in a Q&A format and was in Conformity in 2009. Conformity – HMM Open Forum

Title: “Challenges in Testing”, Subtitle: “Pre-Pulse Voltage in the HBM ESD Model” this is from 2008. Conformity – Pre Pulse Voltage

“System Level ESD Testing Part I: The Waveforms” from 2007. Conformity – System Series 1

“System Level ESD Testing Part II: The est Setup” from 2007 Conformity – System Series 2



“Transmission Line Pulse (TLP) is an Effective Analysis Tool for ESD”, November 2007 available at


EE Times Desinglines

“Meaning of IEC 61000-4-2 ESD Testing On Components” from ~2008 . 


In Compliance

“HBM Pin Combinations” A discussion of when to use Table 2A or Table 2B pin combinations, from November 30, 2019,

“ESDA Working Group 14, System Level ESD”, A discussion of Cable Discharge Event (CDE), from August 30, 2019,

“Simulating Small Device CDM Using Spice”, with Marty Johnson and Scott Ward,  from August 1, 2010,

“CDM Testing of Small Integrated Circuits”, with Marty Johnson and Scott Ward, from June 1, 2010,

“CDM Currents for Small Integrated Circuits”, with Marty Johnson and Scott Ward, from May 1, 2010,


Electronic Design

“Take The Stress Out Of Measuring IEC 61000-4-2 Stress Levels In Portable Devices”