The qualification requirements for integrated circuits for both JEDEC  and the Automotive Electronics Council (AEC) , require ESD testing for both Human Body Model (HBM) and Charged Device Model (CDM). Despite this requirement, examination of integrated circuit datasheets often does not include ESD data, and when they do it is overwhelmingly HBM data, with CDM data seldom included. The Electrostatic Discharge Association’s device testing working group 5.0 found the lack of ESD data, and especially the lack of CDM data troubling enough that it recently published a Standard Practice Document  recommending a format for reporting ESD data in datasheets. In the recommended format the CDM data format was placed before the HBM data format, and that was not just due to alphabetical order. It was to emphasize the importance of CDM data. The lower representation of CDM with respect to HBM is also reflected in Minotaur Labs experience. We receive about twice as many requests for HBM testing as for CDM testing.
So, why perform CDM testing if the industry appears to treat it as less important than HBM? This blog post will try to explain why CDM represents a real threat to integrated circuits in a modern manufacturing environment. We will start with a very traditional explanation of a CDM event, but then will discuss how this relates to a today’s manufacturing environment.
2 Classic CDM Event
The classic example of a CDM event is shown in Figure 1, a shipping tube of integrated circuits is dumped onto a grounded metal bench. Depending on the material of the integrated circuit (IC) and the anti-static properties of the shipping tube the IC can become charged with value Q. The voltage of the integrated circuit depends on the charge on the IC and its capacitance with respect to the metal table, CDUT. Since the capacitance between the IC and the table’s surface is likely small, pF range, the IC to table voltage can become quite large, hundreds of volts.
As the IC drops toward the table CDUT will get larger while VDUT gets smaller. If VDUT started at hundreds of volts there will likely be an air breakdown between the IC and the table top before contact is made. The nature of the discharge can be estimated with a simple LCR circuit. We expect the capacitance to be small, so we will assume 1 pF. There will also be inductance. The inductance will be for both the leads on the IC as well as inductance of the arc. Using the rule of thumb for inductance of a trace being 1 nH per mm we will assume a 1 nH inductance. We expect the metal resistance of the table and the IC to be quite small, so that arc resistance will dominate. Arc resistance for a small spark is often on the order of about 20 ohms. From this we can do a SPICE simulation to give an estimate of a CDM event, which is shown in Figure 2. What we see is an extremely fast event, lasting less than half a nano second, but having a current approaching two amperes.
This result is very similar to the current and time durations of currents in the CDM test and can definitely damage integrated circuits. It is fair to ask, however, who in a modern manufacturing environment dumps a shipping tube of ICs onto a metal table. The answer is of course, no one, but the current pulse above is very similar to what can be expected with modern manufacturing methods.
3 CDM in Modern Assemble Operations
The heart of most circuit board assembly operations is the “Pick and Place” machine. These robotic machines use vacuum pickup heads to grab surface mount devices, including integrated circuits, resistors, capacitors and other components and place them on a circuit board which has already had solder past applied to bond pads. For economic reasons Pick and Place machines must work at high speed. If you are not familiar with these machines it is instructive to watch a video of the machines in action. One that I particularly like is at https://www.youtube.com/watch?v=S8qkaTsr2_o. A more comprehensive overview of the board assembly process is available at https://www.youtube.com/watch?v=BepAMlrJwXI.
The bottom line for CDM is that with machines with a large number of moving parts it is very easy for charge to build up either on the circuit board or on an IC being moved from tape and reel, shipping tubes or shipping trays, to the circuit board. Manufacturers of Pick and Place machines go to great lengths to prevent charge buildup in their machines, but with so many mechanical parts moving so quickly, some charge buildup is inevitable.
The question is then, do we expect the ESD events in a Pick and Place machine to be similar to what we discussed earlier? Figure 3 shows a cartoon of a Pick and Place machine in action. The situation is very similar to the scenario in Figure 1. If the IC has become charged a CDM pulse similar to that shown in Figure 2 could occur. The biggest difference is that since the IC is being placed flat on the circuit board surface the capacitance is likely larger than a corner of an IC touching down first.
An important thing to remember is that the IC need not be charged for a CDM event to occur. A circuit board that is charged will stress the IC in the same way as if the IC is charged. The only difference is that if the board is charged positive with respect to the IC it creates the same stress as if the board were grounded and the IC was charged negative. The severity of a CDM event depends on the following factors; the relative potentials between the two objects when the discharge occurs, the capacitance between the IC and the circuit board and the impedance, resistive and inductive, between the circuit board and the IC.
In summary, any time an integrated circuit makes metal to metal contact with an object at a different potential a CDM event will occur. This type of event is much more prevalent in a modern manufacturing environment than a person touching the IC. Verifying the CDM robustness of an IC is therefore very important for ensuring that it will be a robust component during manufacture.
 JESD47I.01 “Stress-Test-Driven Qualification of Integrated Circuits”
 AEC – Q100 – REV-H “Failure Mechanism Based Stress Test Qualification for Integrated Circuits”
 ANSI/ESD SP5.0-2018 “Reporting ESD Withstand Levels on Datasheets”